At the 90 nm node and beyond, the strained silicon technology has become a fundamental one, which improves performances of MOSFET devices by suppressing short channel effects and enhancing the mobility of carriers. In the strained silicon technology, various stress applying techniques, such as STI, SPT, SiGe embedded source and drain, stressed metallic gate, and Contact Etching Stop Layer (CESL), have been proposed. The stress is applied to a channel region by any of these techniques, so as to improve the carrier mobility, and thus to enhance the drive capability.
Among those techniques, the SiGe embedded source and drain technique is gradually adopted by most CMOS manufactures at the 90 nm node and beyond, where compressive stress is provided to press the channel in order to improve the MOSFET performances by dry-etching the source and drain and then epitaxially growing SiGe. Some companies make further developments in etching the source and drain even at the 60 nm node and beyond.
As shown in FIG. 1, on a substrate 1 having Shallow Trench Isolation (STI) 1A formed therein, a gate stack 2 comprising a gate dielectric layer 2A and a gate conductor layer 2B is formed. A gate spacer 3 is formed to surround the gate stack 2. An active region surrounded by the STI 1A is dry-etched with the gate spacer 3 as a mask. For example, anisotropic dry-etching, such as plasma etching and reactive ion etching, can be performed on the substrate 1 around the gate spacer 3, resulting in first source/drain grooves 1B. Here, two dashed lines crossing each other indicates that two (111) crystal faces intersect each other at a line which is indicated as a point A1 in the sectional view of FIG. 1. In a later wet-etching process, a wet-etching solution may have a greater etching rate at a (110) or (100) crystal face as compared with the (111) crystal faces. As a result, the etching will stop at the (111) crystal faces and also their intersection lines A1. The first grooves 1B have respective side walls (parallel to, and preferably aligned with, respective side walls of the gate spacer 3) apart from the respective intersection lines A1 at a distance of a1.
Then, as shown in FIG. 2, the first source/drain grooves 1B are further etched by a wet-etching solution (e.g., a TMAH solution) which is anisotropic to respective lattice orientations of the substrate, resulting in second source/drain grooves 1C with a Sigma (Σ)-shaped profile. Here, the etching solution also etches bottom portions of the first grooves 1B downward while etching the first grooves 1B laterally to the lines A1, so that bottom portions of the second grooves 1C are lower than the bottom portions of the first grooves 1B by a distance of b1. As shown in FIGS. 1 and 2, the distance a1 substantially determines a recess extent of the Σ-shaped source/drain grooves 1C into a channel region and thus a magnitude of stress applied to the channel region by SiGe and/or SiC epitaxially grown later. Further, the distance b1 substantially determines a depth of the grooves and thus the quality of the stressed SiGe and/or SiC source/drain regions epitaxially grown later.
Subsequently, SiGe and/or SiC is epitaxially grown in the Σ-shaped grooves 1C. Such Σ-shaped grooves are closer to the channel region and cause fewer defects in the later epitaxy process as compared with normal grooves, which helps improving the MOSFET performances.
However, in the prior art process as described above, because the finally formed Σ-shaped grooves 1C are relatively distant from the channel region, application of the stress from the stressed SiGe and/or SiC source/drain regions to the channel region is done over a relatively long distance. Therefore, the channel region has limited improvement in stress. On the other hand, the grooves 1B have their profile significantly different from the profile of the Σ-shaped grooves 1C. The difference between the profile of the grooves 1B and the profile of the Σ-shaped grooves 1C is represented by the distance a1. The distance a1 substantially determines the time required for etching the grooves 1B to form the Σ-shaped source/drain grooves 1C. Because the distance a1 is relatively great, the process of wet-etching the grooves 1B to form the grooves 1C requires either an increased etching rate or an increased etching time, both of which will cause the distance b1 increased unnecessarily, and thus increase the defects at the bottom portions of the grooves 1C and degrade the quality of the epitaxial SiGe and/or SIC.